The present invention relates to flash memories, and more specifically, to a flash memory having alterable erase sector size, such that virtual separation of data and code in a physical bank of flash memory can occur. Further, with two or more physical banks of memory, multiple concurrent operations can occur.
Flash memories have emerged in the art in recent years as an important nonvolatile memory which combines the advantages of EPROM density with EEPROM electrical eraseability.
Flash memories are so named because a plurality of memory cells in a block or sector are erased at the same time. Thereafter, selected bits, bytes, or words are programmed. Flash memories have been used to store program code and data. For storage of data, it is desirable to have the sector size small, so that only a small number of bits of memory cells are erased and then programmed. On the other hand, for storage of program code, it is desirable to have the sector size large, so that a large number of memory cells are erased at the same time. It is further desirable to have a plurality of physically separate banks of memory cells with one bank for storing program code and the other for storing data. Thus, two operations, such as read from program bank while writing to the data bank can occur at the same time. In addition, with the two banks of memories storing different types of information (program code vs. data) thereby requiring different erase sector sizes, it becomes desirable to have two physical banks of flash memories with each memory bank having the option of a unique erase sector size.
Thus, in the prior art a flash bank memory system has multiple banks of memory: one to store program or code and the other to store data. The banks are physically separate, i.e. different physical locations within the system (die) and are addressed by different internal address lines. In addition, each bank has separate bit lines, allowing for two concurrent operation, such as simultaneous read from the code bank and write to the data bank.
However, a significant disadvantage of this prior art flash bank memory system arises since different applications often require different amounts of storage in each of the banks. For example, one application may require a memory bank in which one bank has a storage density of 7 Megabits, while the other bank has a storage density of only 1 Megabits. On the other hand, another application may require a memory bank in which one bank has a storage density of 6 Megabits, while the other bank has a storage density of 2 Megabits. This has necessitated the manufacturer of the memory system to maintain an inventory of different sizes of the memory banks.
FIG. 1 represents a flash memory system 1 of the prior art. In the flash memory 1 of FIG. 1, there are two different sized memory banks 2a and 2b. For example, memory bank 2a may be a 1 Megabit memory bank, with a minimum erase sector size of 4K bytes, whereas memory bank 2b is a 7 Megabit memory bank with an erase sector size of 32K byte sectors, each byte comprising 8 bits. Often memory bank 2a will consist of boot and parameter blocks, e.g. 16K byte sector plus 8K byte sectors etc.
Memory bank 2b has a {overscore (C)}{overscore (E)}, i.e. chip enable, line and a {overscore (W)}{overscore (E)}, i.e. write enable, line. Further the memory banks 2a and 2b are physically separated using different address lines, i.e. address bus 3, consisting of memory address bits A0-A18. Although the memory banks 2a and 2b are physically separate, they may be virtually continuous in the address range. Thus, for example, the memory bank 2a can be addressed in a different address space, from the memory bank 2b, within the common address range A0-A18. It is important to note that each memory bank 2a and 2b has separate address line latches and bit lines.
Typically, program or code is stored in one of the memory banks, e.g. memory bank 2b, while data is stored in the other memory bank, e.g. memory bank 2a. As a result, it is possible to perform concurrent operations on each bank. That is, it is possible, for example, to write data to memory bank 2a while concurrently reading program or code from memory bank 2b. The program or code read from memory bank 2b can be the code to control the write operation of data to the other memory bank 2a. 
In operation, one memory bank will be written with data while the other will store the program which is read for execution by the controller. However, as described above, for this type of flash memory system, a problem emerges in requiring specific sized memory banks for specific applications. Therefore, for these applications that require specific sized memory banks, different memories have to be fabricated, and inventoried. See also U.S. Pat. No. 5,867,430 for a disclosure of two banks with the ability to perform simultaneous operations on the two banks concurrently.
Flash memories responsive to Software Data Protect (SDP) Commands are also well known in the art. In fact, the SDP Commands are standardized by the JEDEC organization (JEDEC Standard 21-C). In a SDP Command, certain signals supplied on either the address bus and/or the data bus to a byte alterable or flash EEPROM nonvolatile memory is interpreted by the nonvolatile memory to perform certain functions commands, such as erase or program (which must be precede by erase for a write operation). Thus, within the nonvolatile memory, there are latches to store the signals from the address and data bus, a decoder to decode the signal stored in the address latch and a control circuitry responsive to the decoder to control the operation of the nonvolatile memory, such as program or erase.
A flash memory comprises an address bus, a data bus, and one or more arrays of addressable nonvolatile memory cells, connected to the address bus and the data bus. Latches store signals supplied from the address bus and the data bus. A decoder decodes the signal stored in the latch, and in response to a first signal decoded for partitioning the array of memory cells into a plurality of first sectors each having a first size, and in response to a second signal decoded for partitioning the array of memory cells into a plurality of second sectors each of a second size, e.g. blocks, different from the first size. A control circuitry controls the erasing of a first or a second sector of the memory array in response to the first or second signal decoded.